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Stitching capacitor and pcb stackup regarding ADM2582E

Question asked by failsafe on Sep 19, 2011
Latest reply on Oct 17, 2011 by ColmR

Hello Colm,

          I am desiging a embedded circuit and the communication interface uses the ADM2582E.  I have purchased the evaluation kit and it works splendidly in the lab.  I have also read the datasheet, Evaluation Board User Guide and AN-0971.  All great reads.  I am looking for some clarification on the PCB stackup and design implemented in the evaluation board.

 

First I wanted to make sure I got the stackup layers correct:

Top: Ground Pour w/split for isolation

2nd Layer:  VCC pour  w/ floating capacitor structure

3rd:  Signal layer

4th: Signal layer

5th:  Not exactly sure?  Huge pour but doesnt look like its tied to any ground

Bottom:  Ground layer

 

Is this correct?  Also can you touch base on the design considerations and why this particular stackup was constructed.

I am mostly curious about a couple of things regarding that: 

 

1)  On the 2nd layer, is my understanding of the floating capacitor correct.  Is it better to integrate the floating capacitor structure on the same plane as VCC instead of giving it its own layer? It seems to me that layers 3 and 4 could be combined if you didnt need to worry about test points(final design).  This would free up an entire layer for just the top/bottom plate of the stitching capacitor.  In that scenario should the top/bottom plates be moved to a different layer or are they better implmented where the are?

 

2) In application note AN-0971 it says to reduce the distance between the power and ground plates by as much as possible (down to a tested 4mil spacing) in order to reduce noise on the internal power and ground planes.  It seems to me that on the refernece design there is quite a bit more spacing then that between layer 2 (VCC) and layer 9 (GND).  Layer 1 (GND) and layer 2 (VCC) do seem to be quite close though.  Was this intentional?

 

3)  Can you tell me what role Layer 5 plays in the design.

 

4)  Lastly, your design workss very well.   Honestly I am going to try to copy as much of it as I can as long as it all makes sense to me first.  What concerns me though is how the isolated rs-485 transciever will work when it is incorporated into a much larger pcb/circuit.  Is there any helpful design rules that you could share when making the move from an "isolated" design like your evaluation board to an integrated design with multiple microcontrollers/clock sources and standalone ADCs?

 

I am quite confident with your help and some hard work on my end the final product will meet or exceed my EMI requirements.  I am just trying to gather as much helpful knowledge before implementation due to the high cost of FCC testing.  I appreciate any and all help you can provide.

Thank you,

Karl Bowers

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