I am trying to rebuild the reference design that runs on the ZC706 for the AD9371. I believe I've got all the modules downloaded correctly and Vivado does build the block design however Vivado reports back that it could not find bus definition for the interface: up_ch_x and a few others. Reviewing the sources in the Hierarchy the axi_hpx_interconnect is locked and greyed out (not sure why).
The design does route (build), but doesn't meet timing and will not create a .bit file. I'm assuming the .bit file not being generated is due to not having a JESD204B license (I only have an eval licence).
Again, this is just the source files not edited so I would have thought things like these warnings and errors would not be presented. Any insights into these issues?