I am using ADV8005 TTL input to capture digital video from FPGA. Inside ADV8005 I am only using the following simple data path:
TTL input (48bit mode) to primary input channel. This is then direct connected to HDMI TX1 and HDMI TX2 output blocks.
Video input is 4K@29.97fps (3840x2160 active pixel). Video input clock is 148.35 MHz. Video data is 2x 2x 10-bit interleaved 4:2:2. Data is input on a two pixel per clock cycle mode identical to ADV7619 output when processing 4K video. This requires pixel clock doubling inside of ADV8005.
My ADV8005 settings:
p_inp_chan_sel is set to 'b10, vid_format_sel is set to 'h0F, tx1_inp_sel is set to 'h00, tx2_inp_sel is set to 'h00.
I can see the video and my 4K HDMI monitor detects correct syncs but tells me that video format is 1920x2160p. This is because ADV8005 HDMI TX output clock is 148.35MHz only (we did measure it). It has to be 296.07 MHz in this case.
My simple question now is how to configure ADV8005 that it doubles video input port clock for internal processing and HDMI TX outputs ?
ADV8005 UG-707 says that input port clock is set based on vid_in_id. However, there is no vid_in_id listed in UG-707 which corresponds to 3840x2160p_30.
We assume that ADV7619 output could be directly connected to ADV8005 TTL digital video input. If ADV7619 is configured for 4K video reception, how has ADV8005 to be configured to output same video again on its HDMI TX ports?