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Hi,  I am using ADP-121 LDO in my GPS receiver design. The input is 3.3V and output is 3.0V. I have tied the ENABLE pin of the LDO to the reset signal from the supervisory circuit. When I power ON my board, the 3.3V domain comes up. The 3.0V domain comes

Question asked by Sudhir on Feb 15, 2017
Latest reply on Feb 15, 2017 by Migs

The LDO output during the reset assertion is captured on an oscilloscope and attached

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