I am just starting out with an fmcomm3 eval board and the ZC706. I would like to use the MathWorks Workflow Advisor reference design tools to create a Vivado project with explicit locations to insert RX and TX custom IP, as well as to use with the HDL Coder tools. However, that reference design in the github repo appears to require Vivado 2015.2.1, which does not appear to be available from Xilinx currently--the Vivado 2015.2 Update 1 file is listed in their downloads section, but gives an error that the file is not available when I try to download it.
I will contact Xilinx to see if I can get that update file, however I am wondering if there is any way I can build the Vivado project in that repo with any other version of Vivado? I have tried 2015.2 and that gave strange results with a lot of unconnected ports. I would appreciate any help with this. Also, many thanks for the great documentation around this part.