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Analog fine delay in HMC7044

Question asked by kiranvg@gmail.com on Feb 14, 2017
Latest reply on Feb 17, 2017 by kpeker

Hi,

I am using HMC7044 for clock distribution in one of my applications. The frequency details are as below.

PLL1 - disabled

PLL2 - enabled

input of 100MHz through OSCIN pins.

Fvco = 3GHz

Divider is 41 to get an Fclkout = 71.42857MHz.

I am planning to use analog fine delay feature of the HMC7044 to take care of delays due to different trace lengths.

The datasheet of HMC7044 says for analog fine delay min is 135ps and max is 670ps with a step resolution of 25ps, and a maximum of 24 delays steps are possible.

But if I do 25ps*24steps = 600ps which is greater than 670-135 = 535ps.

Even if I take the first delay step is 135ps, then also 25*23 = 575ps which is not matching 535ps.

Hence I would like to know if 25ps is the approximate delay resolution or it is exact?

If it is approximate, what is the exact delay resolution?

Also does this fine delay vary with Fvco or Fclkout?

If yes how to calculate this delay for my Fclkout mentioned above?

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