We want to verify the multi-chip baseband synchronization for 6 ad9364's in our custom hardware. We have connected 6 gpios to the respective sync pins of 6 ad9364's. We have modified SDK code for synchronization as follows
ad9361_do_mcs(ad9361_phy,ad9361_phy_b); //ad9361_phy is master others slave
To verify that all DATA_CLK signals are in sync we are using chipscope. We are using the axi_ad9361_5/inst/i_dev_if/i_clk/clk as chipscope sampling clock. and monitoring all the axi_ad9361_*/inst/i_dev_if/i_clk/clk.
We are setting rx_samp_freq of ad9361_5 to 30.72MHz and all others to 15.36MHz.
Then we are running multichip synchronization code.
All the axi_ad9361_*/inst/i_dev_if/i_clk/clk get synced but there is a 90degree phase shift in one random ad9361 ip out of the 6. So actually 4 get synced but 1 does not. We need inputs on where we are getting this all wrong.
Is there any other method to verify the synchronization other than probing on hardware(we do not have the provision of test points on DATA_CLK signal).