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AD9250: JESD204B SYNC NG errors reported by FPGA connected to AD9250 through JESD204B over temperature.

Question asked by SKBY on Feb 13, 2017
Latest reply on Mar 16, 2017 by SKBY

Dear Experts,

 

My customer is facing the following issue. Could you please help my customer to investigate and/or fix the issue?

Please see below and the attached file. Moreover, could you please reply to the following questions?

 

1. Issue description:
1) AD9250 was connected to Xilinx FPGA through JESD204B Subclass 1 with Reference clock and SYSREF clock..

 

2) Temperature tests:
According to the following system-external temperature conditions, the Xilinx FPGA reported the following SYNC-NG errors or not.
2-1) At about 10[degree C] (Ta = about 40[degree C]): The following errors were reported by the FPGA.
2-2) At more or less than 10[degree C] (Ta = about 40[degree C]): The following error were NOT reported by the FPGA.
[The errors reported by the FPGA]:
a) Unexpected K-character(s) received.
b) Disparity Error(s) received
c) Not in Table Error(s) received
Note: The above external temperature was measured outside of the system chassis (case). So, the ambient temperature (Ta) as specified by the AD9250 datasheet will be about 30[degree C] more than the above external temperature. Therefore, when the above external temperature was 10[degree C], the Ta more close to the AD9250 will be about 40[degree C].

 

3) The Realign option tests with some temperature cycles:
3-1) Common test conditions:
a) Before the test, the external temperature was 45[degree C] (Ta = about 75[degree C]).
b) The external temperature was changed from the 45[degree C] to -10[degree C] while the test process.

 

3-2) Test#1 without the Realign option:
3-2-1) Test condition:
a) The Realign option in AD9250 JESD204B Configuration register located at 0x3A was disabled.
3-2-2) Test results:
a) When the external temperature was more than 10[degree C] (Ta = about 40[degree C]), the FPGA did NOT report any error.
b) When the external temperature was about 10[degree C], the FPGA reported the above errors.
c) When the external temperature was less than 10[degree C], the FPGA reported the above errors. The errors were not fixed.

 

3-3) Test#2 with the Realign option:
3-3-1) Test condition:
a) The Realign option in AD9250 JESD204B Configuration register located at 0x3A was enabled.
3-3-2) Test results:
a) When the external temperature was more than 10[degree C] (Ta = about 40[degree C]), the FPGA did NOT report any error.
b) When the external temperature was about 10[degree C], the FPGA reported the above errors.
c) When the external temperature was less than 10[degree C], the FPGA did NOT report the above errors again. The errors were fixed.

 

4) Eye pattern measurements with AD9250 test pattern generations:
The eye pattern of JESD204B outputs connected to 8B test pattern generator through 8B/10B encoder in AD9250 was worse than one directly connected to 10B test pattern generator without 8B/10B converter in AD9250.

 

5) Other conditions:
My customer has found the above errors with 10 AD9250 boards.


2. Questions from my customer:
Could you please reply to the following questions?

 

Q1: Does ADI know the above temperature issue at Ta = about 40[degree C] with AD9250?

 

Q2: Could you please advise my customer about how to investigate and/or fix the above error issue over the temperature?

 

Q3: When the PLL built in AD9250 is locked, what is the frequency accuracy [ppm] of the PLL/VCO built in AD9250?


Q4: After the hardware reset in AD9250 is de-asserted to high level, CLK and SYSREF signals are NOT inputted to AD9250 for a while. Moreover, when the VCO frequency in AD9250 was shifted to any abnormal frequency value, can AD9250 have any way to report the abnormal frequency locking status?

 

Q5: Can ADI guess the reason why the eye pattern in the 8B test pattern test with 8B/10B encoder in AD9250 was worse than the 10B test pattern test without 8B/10B encoder in AD9250?

 

Q6: “Clock adjustment” procedure has been described in JESD204B Configuration of p.44 of AD9250 datasheet Rev.C.
What does “Clock adjustment” procedure in AD9250 do?


Thanks and regards.

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