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ADV7604 HDMI signal LLC clock output and data output questions

Question asked by Sam.S on Feb 9, 2017
Latest reply on Feb 13, 2017 by DerekBurke

Our customers have used the ADV7604 that designed in their product, and the product have MP about half year ago.

Recently, their factory responsed issue that some products devices HDMI 1600x 1200 timing have picture tremble/jitter issue by vertical direction in dot moire pattern or text pattern, and the date code of ADV7604 is newer than before production.


We recommend that customers try to adjust the LLC_DLL_PHASE register is somewhat helpful, some machine can be transferred well!


But customer also asked about this register "LLC_DLL_PHASE" some of the problems:
RD use oscilloscope measurement output data and clock waveform, found to have the following matters
1. When the LLC_DLL phase value is set to 6,7,8 when the high time becomes small (maximum voltage only 2.59V), transferred to 22,23,24,26 when the low time smaller.
2. Value transferred to 7 when the setup time is almost 0, so the screen has noise, on this point, the customer can understand.
3. When the value transferred to 23 setup time 1.55ns is in line with specifications, but the picture has noise, this customer can not understand.
So our customers would like to ask the following questions,


1. Why adjust the LLC_DLL phase value Clock amplitude will be so much change.


2. Phase7 setup time is almost 0, the screen has noise. Phase 9 setup time is very small (<0.3ns), but no noise. How to explain this?


3. Phase 23 has noise, but timing to meet specifications, which parameters may affect? Whether to provide customers with RD check.
In addition, our customers would like to know, that the LLC_DLL_PHASE register of ADV7604 for LLC DLL phase adjustment,
Is the timing of the LLC output cycle of this timing is divided into 32 equal parts to adjust, or
The phase adjustment value of each LSB can be calculated according to a formula that?


Below are 1630 and 1602 date code adjust LLC_DLL_PHASE result:


ADV7604 LLC_DLL_PHASE adjust result

In 1602 date code, Phase 22 / 23 / 24 is good phase result, but In 1630 date code, Phase 22~24 have problem,

to measure the clock output and data output waveform, the sampling point should be in data high region (it's should be relatively safe region), but it have no good sampling result as not we expected.


Would you please help to provide the answer or advised.


Thank you!