I have system that has multiple sensors, each outputting an analog signal that needs to be sampled using an ADC at perhaps 16-bits/sample at a 100MHz rate.
Unfortunately, a quirk of each sensor is that it needs to be reset from time-to-time due to drift. As such, there is a discontinuity in output for a period of time during the reset stage that needs to be corrected for by ‘stitching’ i.e. data interpolation for that period of time from just before that reset to that immediately following the reset.
The signal needs to be stitched and acted-upon in the FPGA domain for purposes of very fast feedback and control.
As a proof-of-concept, an ARRadio board will be used along with a Terasic Arrow SocKit dev board, as it apparently has the best support for Altera+ADC+IIO, and since the IIO stack is needed for other purposes other than stitching. I am aware that the ARRadio is not ideal for this task e.g 12-bit ADCs, built for RF, etc., but I want to focus on the stitching aspect in the FPGA domain for now.
After inspecting the Analog Devices HDL source code it is unclear how to tap the raw data from the ADC, for stitching and then feeding the stitched stream downstream to its usual paths, so I’m looking for suggestions on how to proceed. Are there any examples for doing stitching or similar raw data manipulation while in the FPGA domain? Barring that, which HDL module should I look at for doing that? Would that be module axi_ad9361_rx_channel() with adc_data and adc_data_q, or something more upstream or downstream?