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AD9162 stuck in Code Group Sync

Question asked by bpoladian on Feb 8, 2017
Latest reply on Feb 6, 2018 by jerry_12345

I've got an AD9162 EVM board attached to a Kintex7, using Xilinx's JESD204B IP.  The AD9162 is constantly asserting the SYNC_N signal, and reading back using software shows that only lanes 2 and 3 are getting Code Group Sync.  I think this means that the DAC is configured to expect the correct SERDES frequency, and that my FPGA is outputting data correctly.  I'm running a 3686.4MHz DAC clock, a 4.8MHz SYSREF, interpolation of 3, and a lane rate of 6.144Gbps.  I have probed the SERDES lanes at the decoupling capacitors near the AD9162, and all looks well.  What can I check?  I've used both the provided ACE software and my own software following the startup procedure in the datasheet, both with similar results.  I can see that the PLLs are locking.  I am seeing bad disparity on 3 of the lanes, including the two lanes that are getting CGS.  Any ideas?

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