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Reducing SW datarate below AD9361 capabilities

Question asked by LeroyKii on Feb 7, 2017
Latest reply on Feb 9, 2017 by LeroyKii

Hi everybody,
(Picozed SDR + breakout carrier)


The minimum datarate achievable using Picozed seems to be 2.084 MSPS, that can be reduced to 521 KSPS configuring AD9361 FIR accordingly. Anyhow we still need to reduce that value quite a lot.

In the software subcommunity they told me the proper way to proceed would be to decimate/interpolate either in SW or FPGA.

Thinking about transmission and interpolating within the FPGA:

  • Our idea to achieve interpolation (interpolation factor = X) is to add X-1 zeros between every sample and redesign the AD9361 FIR so the replicas are eliminated.
  • About control signals: adding zeros would mean to "let one of every X read signals to reach fifo_rd_en" so the AD93161 can obtain a new fifo_rd_dout value from DMA, meanwhile "the other X-1 reads can be ignored by the dac_dma block, instead returning zeros to the AD9361"****.

**** My guess here is the ARM doesn't really care what the datarate is to fill the DMA kbuffers with new samples. ARM just takes into account if there's any kbuffer free. I mean, ARM is not datarate dependent in any way.


Practical example -> interpolating by 4:

  • SW datarate configuration using libiio drivers -> 2.084 MSPS (AD9361 datarate)
  • 3 of every 4 reads signals from dac are not sent to dac_dma block. Instead they are redirected to a custom block that returns zeros to the AD.
  • That way axi_ad9361_dac_dma block reads samples from DMA at a datarate of 2084/4 = 521 KSPS and this will be the actual datarate that the SW has to process real time.


Does any of this make sense? Am I missing some important step?