I realized on the AD9361 TDD Half Duplex mode.
All right, but I was not satisfied with the switching time of the RX to TX (20 us)
So I decided to configure the FDD 1R1T Full Duplex independent mode with on / off the Tx LO.
To this end, recorded registers:
0x012 == 0x02 (full duplex)
0x013 == 0x01 (fdd)
0x015 == 0x84 (FDD External Control Enable)
But when I recorded registers, I saw that DATA_CLK frequency twice the frequency RX_FRAME,
but in FDD Full Duplex 1R1T mode frequencies of DATA_CLK and RX_FRAME must be the same.
I try to manage the FSM using the ENABLE and TXNRX signals.
Condition ENSM = 8 (RX TDD), but must be equal 10.
I send a txt-file with registers.
What am I doing wrong?
Prompt please register recording algorithm.
Is there a register ready for configuration mode FDD Full Duplex 1R1T independent mode?