Hello, II'm interested in the timeout ALC level (automatic level calibration). What is it and why is it necessary? and whether it is necessary for manual selection of the VCO? (AUTOCAL is disabled)
In my project I need to change the output frequency in increments of 25 MHz in the frequency range 7325 - 7825 MHz, with a switching time of less than 600 microseconds. As a reference frequency of 10 MHz is used, however, since the desired range for the chip will operate in frequency mode frequency multiplication by 2 to the PFD will operate at a frequency of 2.5 MHz. The program ADISIM PLL I calculated that if the width of the loop PLL is equal to 46 kHz, I get the frequency sweep of about 3.5 milliseconds with AUTOCAL enabled, and about 160 microseconds with manual selection of the VCO (AUTOCAL disabled). So I suppose I'll have to work in this mode (manual selection of the VCO) ..
The issue is related to paragraph 7 the chapter "Frequency Update Sequence" which it is written that before recording "Register 0" you must wait 16 cycles ADС
Sorry for my English