Pg 3-100 of ADSP-214xx SHARC Processor Hardware Reference rev 0.3 states "The AMI controller supports DMA with an external data width of 8 bits."
Does the AMI also support 16-bit DMA access? The next statement "The SDRAM/DDR2 controllers support DMA with an external data
width of 16-bits." implied that the AMI cannot do 16-bit DMA transfers.
I know I can set the AMI width for 16-bit access for core driven accesses but I do not want to burn core cycles transferring data when DMA should do it for me automatically.