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ADuC7061 input bias for  ADC

Question asked by Terumasa on Feb 5, 2017
Latest reply on Sep 22, 2017 by barryzhang

Hello

 

ADuC7061   needs  minimum input bias 100mV when gain setting  is >4 .

 

I reffer to https://ez.analog.com/thread/81273.

Above thread says that   this reason is  no-rail to rail of internal PGA and input buffer .

If so,   does  ther other ADC channel except ADC5 also  need   minimum 100mV bias when gain is >4 ?

 

Regards,

Terumasa

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