I am upgrading the AD9467-FMC KC705 reference design from Vivado 2015.2 to 2016.2. I am having difficulty because the adc_clk clock domain is missing in the 2016.2 project. I am adding IP that requires AXI stream and AXI 4 LITE clock converters. The clock converters are not getting a CLOCK_DOMAIN property set for the M_AXI port that should be the adc_clk. Below are the 2015.2 and 2016.2 clock respectively domains.
The MicroBlaze application hangs on a memory access when I try to read/write a port on the clock converter. Is this a known issue with his version of Vivado? I haven't found anything on the web about it?
The system_constr.xdc constraint files are identical.