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ADV7280 HSYNC too short, why?

Question asked by kotula on Feb 3, 2017
Latest reply on Feb 6, 2017 by JeyasudhaMuthuPerumal

Hey guys!

Does anyone have an idea why the HSYNC signal is only two clock cycles short in my case?! (See picture below)

A PAL camera is used.

It is really weird, VSYNC works totally correct, telling me every frame has 288 lines. From HSYNC to next HSYNC it takes 1728 clock cycles, which is correct, too! Only the duration of the HSYNC pulse is anything else than correct.

 

Your recommended init routine: (ADV7280_CUST-VER.4.5.txt)

:Autodetect CVBS Single Ended In Ain 4, YPrPb Out:
delay 10 ;
42 0F 00 ; Exit Power Down Mode [ADV7280 writes begin]
42 00 03 ; CVBS in on AIN4
42 0E 80 ; ADI Required Write
42 9C 00 ; ADI Required Write
42 9C FF ; ADI Required Write
42 0E 00 ; Enter User Sub Map
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable INTRQ output driver
42 17 41 ; Enable SH1
42 1D 40 ; Enable LLC output driver
42 52 CD ; ADI Required Write
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write [ADV7280 writes finished]
56 00 1C ; Power up DACs and PLL [Encoder writes begin]
56 01 00 ; Set Encoder to SD mode
56 80 10 ; SSAF Luma filter enabled, NTSC mode
56 82 C9 ; Step control on, pixel data valid, ped on, PrPb SSAF on, YPrPb out
56 87 20 ; PAL/NTSC autodetect mode enabled
56 88 00 ; 8 bit input enabled [Encoder Writes finished]
End

 

Init routine I used (different values marked bold):

To address 0x42:

                                0x0F, 0x00, // Exit Power Down Mode [ADV7280 writes begin]
                                0x00, 0x03, // CVBS in on AIN4
                                0x0E, 0x80, // ADI Required Write
                                0x9C, 0x00, // ADI Required Write
                                0x9C, 0xFF, // ADI Required Write
                                0x0E, 0x00, // Enter User Sub Map
                                0x6A, 0x00, // HP = HSYNC
                                0x6B, 0x11, // VP = VSYNC
                                0x37, 0xA1, // HSYNC, VSYNC = ACTIVE LOW
                                0x03, 0x0C, // Enable Output signal drivers
                                0x04, 0x07, // Power-up INTRQ, HS & VS pads
                                //0x13, 0x00, // Enable INTRQ output driver --> This doesn't make any sense to me, in the datasheet this register it is said that this is a read only register!! See picture below.
                                0x17, 0x41, // Select SH1 input filter
                                0x1D, 0x40, // Enable LLC
                                0x52, 0xCD, // ADI Required Write
                                0x80, 0x51, // ADI Required Write
                                0x81, 0x51, // ADI Required Write
                                0x82, 0x68 // ADI Required Write

To address 0x56:

                                0x00, 0x1C, // Power up DACs and PLL [Encoder writes begin]
                                0x01, 0x00, // Set Encoder to SD mode
                                0x80, 0x10, // SSAF Luma filter enabled, NTSC mode
                                0x82, 0xC9, // Step control on, pixel data valid, ped on, PrPb SSAF on, YPrPb out
                                0x87, 0x20, // PAL/NTSC autodetect mode enabled
                                0x88, 0x00  // 8 bit input enabled [Encoder Writes finished]

 

Does anyone know what the problem is?

 

 

P.S.: Don't pay attention to the times shown in the pictures, the time is always referecend to a 200MHz clock with the measurement tool I use.

 

Best regards,

Markus

 

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Added:

I now connected a NTSC camera to it, I get the same HSYNC behaviour (HSYNC is too short) but here the number of lines in one frame is 252, although it should be 242. So here is another mistake.

 

I always said HSYNC is too short, what I actually meant is HSYNC is too long, since it is low active! Sorry.

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