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AD-FMCDAQ2-EBZ ADC/DAC Clocking

Question asked by caugusta Employee on Feb 2, 2017
Latest reply on Feb 2, 2017 by rejeesh

 

Hi,

 We have a customer that is trying to figure out how to set the ADC clock to 1 GHz and DAC Clock to 2.8 GHz on the AD-FMCDAQ2-EBZ.  They are plugging this board into a Xilinx KCU105 dev kit.  Our Xilinx FAE is going to be heading there tomorrow to assist.

 

2 concerns:

 The following comment from the wiki page: “The AD9523-1 has two clock banks (see figure 1 in the datasheet), Bank 0: 0-3 & 10-13, and Bank 1: 4-9. The outputs on the different banks need to be integer multiples of each other.” Does this imply that the ADC and DAC clock have to be multiples of one another?

 

  1.  I tthink the AD9144 DAC on this FMC Card achieves 2.8 GHz using interpolation. I think Jefferson Labs may just want to run this as fast as possible. Is my interpretation below correct?

o   At 1x Interpolation, the max speed would be ~ 1x  1000 MHz = 1000 MHz, the DAC clock would have to be set to 1000 MHz

o   At 2x Interpolation, the max speed would be ~ 2x  1000 MHz = 2000 MHz, the DAC clock would have to be set to 2000 MHz

o   At 4x Interpolation, the max speed would be 2.8 GHz, therefore ~ 4x  700 MHz = 2800 MHz, the DAC clock would have to be set to 2800 MHz

o   At 8x Interpolation, the max speed would be 2.8 GHz, therefore ~ 8x  350 MHz = 2800 MHz, the DAC clock would have to be set to 2800 MHz

 

Best regards,

ADI Tech Support

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