Hi, dear ADI engineers, we built an AD9115 prototyping board with following power settings:
AVDD = 3.3V
DVDD = DVDDIO=CVDD=1.8V
The clk signal is from a clk chip's LVCMOS18 output, and we feed DCLKIO to FPGA. The FPGA reconginzed the CLK and output data to DAC, althought the output data's logic level is 1.8V, the DAC did not respond to the data iput, the DAC reconginze all data input as 0s. Have you ever seen this issue before?
The " Data Control" register is set to 0x32 to put DCLKIO as output, is there any other registers we need to notice?
Thank you in advance!
BTW, when we put AVDD=DVDDIO=CVDD=3.3V, the DAC works. But we need to use 1.8V CMOS as the whole bank of our FPGA is 1.8V.