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IP Cores of reference design for FMCDAQ2-EBZ

Question asked by YifanKevinZhu on Feb 1, 2017
Latest reply on Feb 2, 2017 by YifanKevinZhu

I'm currently using FMCDAQ2-EBZ board on Altera FPGA, Arria 10, and when I went through your reference design, I find there are a lot of IP cores which are specially designed by Analog Devices, so I went through the Analog Device website for more detailed information about these IP core, and I can't find them. So, what I want is the detailed description of the following IP cores:
1, avl_adxcvr (Avalon ADXCVR Core)

 

2, axi_adxcvr (AXI ADXCVR Core)

 

3, axi_ad9144 (AXI AD9144 Interface)

 

4, axi_ad9680 (AXI AD9680 Interface)

 

5, util_upack (Channel Unpack Utility)

 

6, axi_dmac (AXI DMA Controller)

 

7, util_adcfifo (ADC FIFO utility) 

 

8, avl_adxcfg (Avalon ADXCFG Core) 

 

And also, I want to make sure, in the reference design of FMCDAQ2-EBA, what is the data flow of ADC and DAV values. How the reference design transmit the ADC values through the Jesd interface and where are these values stored? What kind of format are they organized?

 

Thanks for any helo#

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