we are currently testing AD9144 JESD interface with Xilinx FPGA using Xilinx JESD204B IP core. The test is done on a custom board.
1) AD9144 PHY PRBS7 and PHY PRBS15 tests pass OK, but AD9144 PHY PRBS15 test fails.
2) The JESD link is up, no errors on the link. When FPGA sends sine wave samples over JESD using Xilinx IP, DAC produces the correct sine wave form on the oscilloscope.
AD9144 Datapath PRBS7 and PRBS15 fail.
Our PRBS generator can produce the same output of PRBS generator in https://github.com/analogdevicesinc/hdl/blob/dev/library/axi_ad9144/axi_ad9144_channel.v#L139
We then swap the bytes entering Xilinx IP in the same way that is done in https://github.com/analogdevicesinc/hdl/blob/dev/library/axi_ad9144/axi_ad9144_if.v#L112
Simulation shows that the input of Xilinx JESD IP in our design is the same that is input in the DAQ2 reference design using PRBS test mode.
Any idea on why is the test failing?
Would you please confirm that Analog Devices verified AD9144 PHY PRBS and Datapath PRBS?