Dear Experts,

My customer is considering to choose ADF4355 under the following conditions.

**1, Conditions:**

1) Target chip: ADF4355.

2) REFin frequency: 10.0[MHz].

3) RFout frequency: 510.2928571[MHz] through 744.2928571[MHz] with 6[MHz] step.

That is to say, the following frequency values are required:

510.2928571[MHz], 516.2928571[MHz], 522.2928571[MHz], 528.2928571[MHz], … , 732.2928571[MHz], 738.2928571[MHz], 744.2928571[MHz].

4) Phase noise: Minimum -53[dBc] Target -55[dBc] as the integral value of phase noise at 10[Hz] through 1[MHz] as offset frequency.

**2. Questions from the customer:**

Could you please reply to the following questions?

**Q1:** ADIsimPLL can make simulation for phase noise as [dBc/Hz]. Can ADIsimPLL calculate an integral value of phase noise for the specific frequency bandwidth?

**Q2:** The customer wants to secure one decimal place like 0.1[Hz] order in the RFout frequency of ADF4355. Can ADIsimPLL support one decimal place like 0.1[Hz] order in the RFout frequency of ADF4355 at 510.2928571[MHz] through 744.2928571[MHz]?

*Thanks and regards.*

Q1:ADIsimPLL can make simulation for phase noise as [dBc/Hz]. Can ADIsimPLL calculate an integral value of phase noise for the specific frequency bandwidth?Yes, look on the Report page:

You set the limits of the integration using Edit / Report Options from the main menu, and then use the Phase jitter tab.

Q2:The customer wants to secure one decimal place like 0.1[Hz] order in the RFout frequency of ADF4355. Can ADIsimPLL support one decimal place like 0.1[Hz] order in the RFout frequency of ADF4355 at 510.2928571[MHz] through 744.2928571[MHz]?There seem to be two issues here:

You don't specify this, but given that you are specifying the frequencies to 10^-10, there is a real chance that you want the exact frequency relationship between the reference and the output. If this is the case, my initial calculations suggest this is not possible with the ADF4355, but a ADF4355 expert may be able to achieve it.

If you don't need the exact frequency relationship, you can get within microHz of the wanted frequency. To get exactly 6MHz increments you need MOD2 a multiple of 5. If you set MOD2 = 5000, then to get 510.2928571MHz with a 10MHz Fpd:

INT = 408, FRAC1 = 3930661, FRAC2 = 2295, set the output divider to divide by 8, and you will get a frequency which is 5uHz low, but be able to step in exact 6MHz steps from this. You should check these calculations, I did them quickly.

The title of the phase noise plot in ADIsimPLL is set to 3 significant digits, simply because the phase noise performance doesn't change much within this resolution. If this is an issue we can change it in a later release. The actual frequency at which the phase noise simulation is performed can be found in the left panel:

and by right clicking on this (the 510.2929MHz) you can change the number of displayed digits.