My customer is considering to choose ADF4355 under the following conditions.
1) Target chip: ADF4355.
2) REFin frequency: 10.0[MHz].
3) RFout frequency: 510.2928571[MHz] through 744.2928571[MHz] with 6[MHz] step.
That is to say, the following frequency values are required:
510.2928571[MHz], 516.2928571[MHz], 522.2928571[MHz], 528.2928571[MHz], … , 732.2928571[MHz], 738.2928571[MHz], 744.2928571[MHz].
4) Phase noise: Minimum -53[dBc] Target -55[dBc] as the integral value of phase noise at 10[Hz] through 1[MHz] as offset frequency.
2. Questions from the customer:
Could you please reply to the following questions?
Q1: ADIsimPLL can make simulation for phase noise as [dBc/Hz]. Can ADIsimPLL calculate an integral value of phase noise for the specific frequency bandwidth?
Q2: The customer wants to secure one decimal place like 0.1[Hz] order in the RFout frequency of ADF4355. Can ADIsimPLL support one decimal place like 0.1[Hz] order in the RFout frequency of ADF4355 at 510.2928571[MHz] through 744.2928571[MHz]?
Thanks and regards.