I would like to get the opinion of an applications engineer or another designer that may have already implemented a custom design based upon the AD9914 DDS chip.
- Decoupling - The evaluation board for the AD9914 seems to have 0.1uF capacitors at each power supply pin and a 10uF capacitor for each rail. In general I assume this the recommended configuration, but I am interested if anybody has had any success (or failure) with a different implementation.
- Isolation - Is there a recommendation to isolate the 3V3 and 1V8 analog and digital supply lines? (same question for the AGND and DGND nodes)
Unused chipset features
- PLL - If a design does not make use the internal PLL, what is the proper way to terminate the LOOP_FILTER and REF pins to avoid negatively impacting the operation of the circuit?
- OSK - Should this pin be pulled low (or high) if the OSK function is not being used?
- RAMP GENERATION - I assume that the output signal DROVER can be left open and the two inputs DRCTL and DRHOLD should be pulled low if the ramp generator is not being used. Is this acceptable?
Thanks in advance for the advice!