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Reducing datarate: BIST loopback and AD9361 FIR configuration problem

Question asked by LeroyKii on Jan 31, 2017
Latest reply on Feb 1, 2017 by LeroyKii
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Hi everyone,

 

(PicoZed SDR + breakout carrier)
We are trying to implement a TDMA system, where every slot is 20 ms and 4032 samples are transmitted or received in that time. So we'd ideally need a data rate of 201.6 ksps. And all of those data must be processed in real time.
Well, I've saw that minimum datarate achievable is 521 ksps configuring the filter with "AD936x_LP_180kHz_521kSPS.ftr".

I have several questions about it:

 

1) Is there any possible way to reduce the datarate even more? I guess I always could add a decimation/interpolation blocks into the FPGA, but that sounds like a tough task...


2) If I tried to read (refill) or write (push) blocks of 4032 samples at 1 MSPS and do a little realtime processing (a couple of memcpy's and a few checkings) a lot of underflow and overflow of kbuffers happens. Is the radio not prepared to work with these small buffer sizes?

 

3) I'm using BIST loopback to debug my transmission->reception in the digital domain, and an incremental counter from -2048 to 2047 is being sent and received as shown in the figure:

 

example signalBut when the FIR is configured with the new coefficients to achieve 521 ksps, the signal received looks attenuated and quite noisy:

My assumption is BIST loopback doesn't get along too well with a new FIR config. Am I doing something wrong? or what's actually happening?

Regards,
Leroy

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