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Low phase error/drift between several AD9951

Question asked by tcachat on Jan 30, 2017
Latest reply on Mar 23, 2017 by JLKeip

Dear all,

We have designed, assembled and tested a board containing many AD9951. We have achieved to synthesize frequencies on all outputs. For test purposes we can also select the same frequency on all channel. We need to synchronize all DDS from an external signal: the I/O_UPDATE signal is sent to all DDS simultaneously. We use the SYNC_IN and SYNC_CLK pins to synchronize all DDS to a "master" and it works more or less, except that there is very low phase error/drift between the DDS. The error is of the order of 0.3 ns (1 degree at 10 MHz) and is not so problematic. The drift is of the order of 0.03 ns (0.1 degree at 10 MHz) and is as follows. We let all synthesizers work for some time, then we send a burst of hundreds of I/O_UPDATE signals (every 20 µs or so). During the first 30 pulses the phase of each channel change slowly and then stabilizes.

We have paid much attention to the quality of the clock signals, the length of the different tracks, the clock buffers. We use differential square clocks signals. REFCLK is at 25 MHz, we use the internal PLL x16.

 

In the configuration we use OSK_Enable, SDIO_input_Only, SYNC_CLK_Out_Disable, Automatic_Sync_Enable, AutoClr_Phase_Accum, except for the "master" : OSK_Enable, SDIO_input_Only, AutoClr_Phase_Accum.

REFCLK Multiplier x16, VCO_Range, High_Speed_Sync_Enable.

 

Do you have an idea how we could improve the results?

Thank you

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