Thank you for your reply.am new into this one.i have another one doubt.
1)To configuring the AD9361 using picozed ,one ip core is available
i)how to add AD9361 IP core to this design
I've branched this additional question into a new discussion and moved it into the FPGA section.
For information on how to use Xilinx Vivado IP integrator in general please refer to Vivado 2016.4 - Using IP Integrator.
For specific information on the axi_ad9361 core please refer to AXI_AD9361 [Analog Devices Wiki].
thank you for your guidence.i need the timing diagram for this axi_ad9361 ip core.
Hope you got all the info, that you needed in the following thread: axi_ad9361 ip core
If not, please continue this discussion there, will close this one. Also please avoid creating multiple thread with the same topic.
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