In the datasheet's Figure 69. Single Conversion Mode The nCS line is kept low during the transactions.
But is it ok to take nCS high between transactions? Such as:
- Pull nCS low
- Write 0x01 0x8010 (in one constant sclk rate sequence)
- Pull nCS high
- Wait for a minimum time for adc conversion (Noting that when nCS is high, RDY is high impedance so cant poll on the state of conversion)
- Pull nCS Low
- Write 0x44 0xFFFFFF and at the same time read the 24bit conversion result (or write 0x44 0xFFFFFFFF to read 24bit conversion+status)
- Pull nCS High
and so forth from 1. again. to read the conversion from the next enabled channel.
thanks for any hints