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AD6676 100 - 122,88 MSPS troubleshooting

Question asked by DST_ERA on Jan 27, 2017
Latest reply on Feb 1, 2017 by PMH

Hello,

 

we have succesfully modified reference project for VC707 kit (hdl_2016_r2) and modified AD6676-ebz kits. Now we have working design with two AD6676 with external 200 MHz clock and external 1 MHz SYSREF (both generated from HMC704).

We use No-OS drivers from dev branch.

 

Now we would like set up ADc for external 100MHz clock (then for 122.88MHz). We have modified reference code for Microblaze to print samples from DMA(no-OS/ad6676_ebz.c at dev · analogdevicesinc/no-OS · GitHub ).

The red lines are for highlight code what does configuration of JESD or I'm unsure about.

Comments with DEFAULT values are for comparison for configuration with 200MHz what works fine.

 

...
        SPI_DEVICE_ID,    // spi_device_id
        /* Device Settings */
        100000000UL,    // reference_clk_rate                        - DEFAULT: 200000000UL
        0,                // spi_3_wire
        3200000000UL,    // adc_frequency_hz
        100000000UL,    // intermediate_frequency_hz                - DEFAULT: 250000000UL (see Figure 80)
        MIN_FIF,        // intermediate_frequency_min_hz - depend on Lext
        MAX_FIF,        // intermediate_frequency_max_hz - depend on Lext
        75000000UL,        // bandwidth_hz
        5,                // bandwidth_margin_low_mhz
        5,                // bandwidth_margin_high_mhz
        0,                // bandwidth_margin_if_mhz
        32,                // decimation                                - DEFAULT: 16
        96,                // external_inductance_l_nh                    - DEFAULT: 19
        64,                // idac1_fullscale_adjust
        0,                // use_external_clk_enable
        1,                // adc_frequency_fixed_enable
        1,                // jesd_scrambling_enable
        1,                // jesd_use_lvds_syncb_enable
        0,                // jesd_powerdown_sysref_enable
        1,                // jesd_l_lanes                                - DEFAULT: 2
        16,                // jesd_f_frames_per_multiframe                - DEFAULT: 16
        1,                // shuffler_control
        5,                // shuffler_thresh
        };

/***************************************************************************//**
 * @brief main
 *******************************************************************************/
int main(void) {
    init_platform();
    adc_core ad6676_core;
    ad6676_dev *ad6676_device;
    jesd204_core ad6676_jesd204;
    adxcvr_core ad6676_xcvr;


    ad6676_jesd204.base_addr = AD6676_JESD_BASEADDR;
    ad6676_jesd204.rx_tx_n = 1;
    ad6676_jesd204.octets_per_frame = 4;  // DEFAULT: 1
    ad6676_jesd204.frames_per_multiframe = 32;
    ad6676_jesd204.subclass_mode = 1;
    ad6676_jesd204.sysref_type = EXTERN;
    ad6676_jesd204.gpio_device.device_id = default_init_param.gpio_device_id;
    ad6676_jesd204.gpio_device.type = default_init_param.gpio_type;
    ad6676_jesd204.gpio_sysref = GPIO_JESD204_SYSREF;

    ad6676_xcvr.base_addr = AD6676_ADXCVR_BASEADDR;
    ad6676_xcvr.tx_enable = 0;
    ad6676_xcvr.gth_enable = 0;
    ad6676_xcvr.lpm_enable = 0;
    ad6676_xcvr.out_clk_sel = 4;
    ad6676_xcvr.sys_clk_sel = 0;
    /* AD6676 Page 50 */
    ad6676_xcvr.init_set_rate_enable =  1;  // DEFAULT : 0
    ad6676_xcvr.lane_rate_khz = 4000000;    // DEFAULT : 4000000
    ad6676_xcvr.ref_rate_khz = 100000;   //DEFAULT : 200000
    // set up the device
    ad6676_setup(&ad6676_device, default_init_param);
    ad6676_core.adc_baseaddr = AD6676_CORE_BASEADDR;
    ad6676_core.dmac_baseaddr = AD6676_DMA_BASEADDR;
    ad6676_core.no_of_channels = 2;    //DEFAULT : 2
    ad6676_core.resolution = 16;
    // set up the JESD link and bring up the core
    jesd204_init(ad6676_jesd204);
    adxcvr_init(ad6676_xcvr);
    jesd204_gen_sysref(ad6676_jesd204);
    adc_setup(ad6676_core);
    // check JESD link status
    jesd204_read_status(ad6676_jesd204);

    /* Enable Ramp Test Mode */
    ad6676_spi_write(ad6676_device, AD6676_TEST_GEN, TESTGENMODE_RAMP);
    xil_printf("Start capturing data...\n\r");
    adc_capture(ad6676_core, 64, ADC_DDR_BASEADDR);
    Xil_DCacheInvalidateRange(ADC_DDR_BASEADDR, 64);

    int i;
    u16 Isample, Qsample;
    print("FMC1\n");
    for (i = 0; i < 64; ++i) {
        Isample = Xil_In16(ADC_DDR_BASEADDR + i * 4);
        Qsample = Xil_In16(ADC_DDR_BASEADDR + i * 4 + 2);
        xil_printf("%d: I=%u Q=%u\n", i, Isample, Qsample);
    }
    cleanup_platform();
    return 0;
}

 

Here is output from terminal:

 

AD6676 successfully initialized.
JESD204 initialization done.
XCVR successfully initialized.
ADC Core Initialized (50 MHz).
SYNC STATUS: 0x10000
jesd_status: Link SYNC not achieved!
Start capturing data...
FMC1
0: I=0 Q=5632
1: I=0 Q=0
2: I=0 Q=5632
3: I=0 Q=0
4: I=0 Q=5632
5: I=0 Q=0
6: I=0 Q=5632
7: I=0 Q=0
8: I=0 Q=5632
9: I=0 Q=0
10: I=0 Q=5632
...

 

Obviously there is something wrong with JESD configuration but I don't know what - according to AD6676 datasheet page 50.

 

For external 200Mhz reference clock and default configuration the output is:

AD6676 successfully initialized.
JESD204 initialization done.
XCVR successfully initialized.
ADC Core Initialized (100 MHz).
SYNC STATUS: 0x10000
Start capturing data...

FMC1
0: I=34210 Q=34209
1: I=34211 Q=34210
2: I=34212 Q=34211
3: I=34213 Q=34212
4: I=34214 Q=34213

...

As you see there are correct ramp samples and no errors from initialization phase. We have tried different clocks for 2 lane configuration (above 160MHz) with success.

 

Can someone please help me?

 

Regards,

Daniel

 

 

Some notes:

We have connected signal rx_tvalid (JESD204 IP) to rx_valid (ad6676_core). In reference project it was unconnected.  For what reason?

 

There is possible memory leak in no-os drivers - no-OS/ad6676.c at dev · analogdevicesinc/no-OS · GitHub 

lanes 827, 828 - memory for dev is not freed. I don't know why dynamic memory allocation is used there  so I rewrited it to static usage. I just wanted to point it out.

Outcomes