Hi, we're working with a PicoZed SDR (using AD9361) and have tried to understand how the RSSI is accumulated and when it can be read by looking at the datasheet and searching this forum for similar references but we're still confused.
1. For a TDD application, we are using rssi-restart-mode 2 (restart RSSI algorithm when the AD9361 enters rx mode). If the rx signal is asserted at the beginning of the slot and cleared at the end of slot, is the RSSI wait value used by the AD9361 or does it use only the RSSI delay value at the beginning since there is only one receive packet each slot?
2. Can the user application read the RSSI anytime during that the AD9361 is accumulating the RSSI value and get a valid RSSI value? From the documentation, it would seem that the application should wait until the AD9361 has completed its accumulation, but I want to confirm.
3. If the user application waits until the end of the slot to read the RSSI, then the RSSI value remains in the register even if the accumulation stopped earlier as specified by the RSSI duration value, is that correct? For our configuration, the rx signal is not asserted again until the next slot, so we should be able to read the RSSI value later.
FYI, we can design the PL side to trigger interrupts for specific events during the slot to the PS side to allow our PS software driver to go read the RSSI value in real time.