According to UG-671, after a gain change, the peak overload detection circuit will be in reset for Peak Overload Wait and the power measurement circuit for Settling Delay.
Question -- The above two delays, peak overload wait and RSSI settling delay, happen at the same time in Fast Attack AGC state 1 or one after another?
According to UG-671, upon entering Fast AGC State 2, AD9361 waits for a time equal to Settling Delay minus Energy Detect Count before measuring power. It seems that Peak Overload Wait is excluded. This explanation seems to say that the Settling Delay starts after Peak Overload Wait?