I am attempting to sweep the LO on the ADRF6820 and speed is limited by the '94,208 PFD cycles' required to calibrate the VCO after programming a new PLL frequency.
I have attempted to disable this by setting register address 0x44 to the value 0x0001. After doing so, the PLL no longer locks to the correct frequency. It seems to rail to certain frequencies (700 MHz, 851 MHz...)
I can provide further info of the PLL settings I'm provided but I believe I'm just missing another bit or two that needs to be set.
Perhaps I need to set something in register address 0x45? I couldn't find any info on SIF vs. bandcal or what belongs in the 7 bit VCO band selection.
I have only been setting the desired VCO in register address 0x22.
Any help is greatly appreciated.