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What is rate of dac_clk signal  in axi_ad9371_core of reference design hdl-hdl_2016_r2 for AD9371 board?

Question asked by amdakwar12 on Jan 23, 2017
Latest reply on Feb 2, 2017 by rejeesh

Hi,

I am using hdl-hdl_2016_r2 branch for AD9371 reference design (zc706 platform).

I am trying to add xilinx DUC/DDC complier ip between tx_dma and axi_ad9371_core.

I wish to know details on dac_clk  , dac_valid_i0, dac_enable_i0 signals.

How those signal generated with respective DAC Sampling rate which is 245.78 MSPS?

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