AnsweredAssumed Answered

DAC and ADC Channel signal strength in ad9361 hdl IP

Question asked by Sumeet002 on Jan 23, 2017
Latest reply on Jan 24, 2017 by Sumeet002

Hello,

We are working on a design for two ad9364's and we want to achieve interchip loopback. Rx data from one ad364 to be fed to TX of the second ad9364. We are using fmcomms5 design as reference for Virtex7 Vivado design.

 

Test condition 1: 

we generated a PRBS sequence( 0x3F4 = 0x09 ) in one of the ad9364's and set it in loopback mode 2. We saw a PRBS sequence on the TX output of the ad9364 with signal level upto -42dBm.

 

Test Condition 2:

We generated a PRBS sequence (0x3F4 = 0x09) in 1st ad9364 and connected the adc_data_i0 and adc_data_q0 of first ad9364 hdl IP to dac_data_i0 and dac_data_q0 of the second ad9364 hdl IP(refer attached figure). In this mode we observe the waveform on the TX port of second ad9364 and we see that the waveform is exactly the same as in test condition 1 but the signal level drops by 16dBm. For second ad9364 we configured it in DMA mode and commented the part where it copies data from DDR. We also tested it by giving our own custom data which works fine.

 

What could be the cause of this problem? Any suggestions. We want to to do interchip loopback, is there any other method for this? We need some urgent help. Thank you. rejeesh, larsc, DragosB, tlili

Attachments

Outcomes