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Question asked by Javier on Sep 12, 2011
Latest reply on Sep 13, 2011 by Javier

Hi all, I`m using the evaluation board of AD9910 to generate a chirp signal in no-dwell Ramp Mode (both no-dwell bits). Documentation states that in this mode DROVER signal is a positive pulse of duration two cycles of the DDS clock each time the ramp reaches the upper and lower limits. Checking this signal against the SYNC_CLK signal (J9) it seems the positive pulse has a duration of two cycles of this signal that, in fact, is REFCLK/4. Is that correct?