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AD9371 MCS issue

Question asked by bensonyeung2 on Jan 20, 2017
Latest reply on Mar 24, 2017 by rejeesh
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Hi I was wondering if there is any hardware design issue on SYSREF/DEV CLK signal path which could lead to

AD9371 MCS(Multiple chip syn) failed? I did make sure the custom board was length matched and with diff impedance of 100ohm. I understand the MCS routine expectes a minimum 3 pulses but I guess they need to be properly align up with dev clock?


The UG-992 has information about RF matching but not much on JESD related signal layout tips.