My customer is reviewing the following circuit note, CN-0232. Could you please reply to the following questions?
CN-0232: “Minimizing Spurious Outputs Using a Synthesizer with an Integrated VCO and an External PLL Circuit”.
Q1: According to the above circuit note, the cascaded PLL devices will reduce the spurious level.
Can ADIsimPLL make some simulations with the cascaded PLL devices (ADF4350 + ADF4153) as shown in the above circuit note?
Q2: If you know any way to make some software simulations with the cascaded PLL devices (ADF4350 + ADF4153), could you please advise my customer about it?
Thanks and regards.