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ADG1407 32LFCSP PCB Routing

Question asked by A.Donahue on Jan 17, 2017
Latest reply on Jan 20, 2017 by Davidforde

We're working on a new design and have decided on using the ADG1407BCPZ-REEL7 (32LFCSP Package).  It has a large ground/thermal plane directly underneath and we're running into PCB routing issues trying to keep the differential pairs together while minimizing Blind/Buried Vias and the number of layers used.

 

A couple options we've explored:

1) Routing all analog tracks and immediately diving down to another layer using a via.  Routing to the center to minimize the length the differential pairs are separated. 2 differential pairs are able to be routed per layer (one out each side), thus requiring at least 6-8 layers minimum.  See attached picture.

2) Routing all analog tracks and immediately diving down to another layer using a via.  Routing to the center to minimize the length the differential pairs are separated (routed in the Y direction).  Using Blind Vias to route down to the next layer and then routing in the X direction. See attached picture.

 

How were these chips intended to be routed with the large ground/thermal pad underneath and yet keep the differential pair separation minimized?

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