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Difference in pn monitor in ml605 design and vc707 design of ad9361

Question asked by Sumeet002 on Jan 17, 2017
Latest reply on Feb 2, 2017 by rejeesh

Hello,

We are curious to know why is there a difference between the pn monitor code in the ml605 design (fpga-hdl-xilinx-master) and the vc707 design(github analog device hdl) ? We found that a bit reversal function is used in the ml605 design. Why was it removed in the vc707 design? Was it because of the change in device primitives of iodelay of Virtex6 and Virtex7?

the files we compared were

(github/hdl/library/common/ad_pnmon.v)  and

(fpga_xilinx_master/cf_lib/edk/pcores/axi_ad9361_v1_00_a/hdl/verilog/axi_ad9361_rx_pnmon.v)

Hope to get your feedback soon..larsc tlili DragosB

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