We are curious to know why is there a difference between the pn monitor code in the ml605 design (fpga-hdl-xilinx-master) and the vc707 design(github analog device hdl) ? We found that a bit reversal function is used in the ml605 design. Why was it removed in the vc707 design? Was it because of the change in device primitives of iodelay of Virtex6 and Virtex7?
the files we compared were