I'm developing a AD9284, dual channel fpga based data capture system. In this, I connect the inputs of the AD9284 to the FPGA & capture the data in the fpga fabric using IDDR instance. I'm combining the 2 outputs of the IDDR, storing in a FIFO and transmitting to pc via PCIe.
The hardware settings are as follows:
AD9284 Evaluation board -> Expansion header's LVDS pins on XUPV5 -> XillybusPCIe -> PC
The issue is that everytime I connect input to one of the inputs of the AD9284 evaluation board and terminate the other input with a 50 ohms, I still measure the same signal in both the data points. When I don't connect any input, I get a variation of 1LSB, which is expected. But there seems to be a large "cross talk". I checked the synthesis messages /RTL schematic & everything seems ok there. I'm not setting any SPI registers. The ADC control registers are with their default values, With the same config, when I connect to EVALCZ, the output is as expected .
If I replace the ADC and use a simple counter at 2x rate and pushing it through a DDR_flip flop, then the output values are as expected !.
Am I missing something here ?
Kindly help me with this issue. I've attached the zip file of the xilinx project. The schematic file named xilly_adc contains this design.
Thank you !