I am having difficulty achieving output from the AD9951. Here are the symptoms:
Hardware configuration: I am using a single AD9951 IC, so the synchronization features are not used. SYNC_CLK and SYNC_IN are N/C. IOSYNC is ties to DGND. The clock input is a 20MHz crystal. IOUT and \IOUT are pulled to AVDD through 200 ohm resistors. DAC_RSet is a 3.92k resistor to analog ground. OSK is unused and floating. PWRDWNCTL is tied to DGND.
Software: At startup, I assert RESET to initialize registers. I can program register 0 and register 1 and read them back. I know the communications are working because I can set the PLL successfully, and enable/disable SYNC_CLK at will. Likewise I can turn the crystal on and off.
Issue: When I write a frequency word to register 4, absolutely nothing happens. Both IOUT and \IOUT remain close to ground; the PLL/4 frequency still appears on SYNC_CLK, etc. Current draw remains constant. Multiple IO_UPDATES do nothing. I've tries this with and without auto update of the phase register enabled. Slowing down my SPI bus to 1kbps does not improve anything. Its almost as if the DDS core is happy, but the DAC is powered down for some reason. However, none of the power down bits in CFR1 are set.
Questions: I've seen in posts here that these chips seem to work if I strip IOSYNC to SYNC_CLK - is this necessary? Why would that help? Also, must my IOUPDATE strobe be coincident with SYNC_CLK to be recognized? If so, why does this work for registers 0 and 1, and not register 4?
If anyone has ever gotten one of these to work with a dsPIC, could you please post the code and some schematics?