in AD9361 for rfpll (tx/rx ) frequency loading and vco calibration it is taking 370us. We are using non os drivers version 2015. SPI is running on 12mhz. The time it is taking from set_tx_lo frequency to spi writes is 240us and vco calibration time is 120us. As per discussions in the E-zone the time for pll lock for new frequency is spi witre time+ vco cal time. Is there a process delay in the frequency loading routine, apart from the SPI writes time.Please clarify.