We are using AD7621 which is configured to use as serial interface. FIN1031 deriver is connected to translate SCLK and SDOUT LVTTL signal level to LVDS level for SPARTAN6 FPGA and FIN1032 receiver translates CNVST LVTTL signal level from SPARTAN6 FPGA to AD7621 LVDS level. what we have noticed is AD7621 serial output reading is same for blocks of conversions up to 10 samples. But when we configured in parallel interface the output data is read correctly. Can you please let me know if there is any know issue with the AD7621 serial interface? Is it due to the FIN1031 and FIN1032?