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logical to physical lane mapping in ad-9144 of ad-fmcdaq2 board

Question asked by appu.b on Jan 16, 2017


I am using AD-FMCDAQ2-EBZ card with vc707, i have got demo setup up and running. I was going through the c code and understood that for ad9144 there is a logical to physical lane mapping. but i am confused with order given.

ad9144_init_param default_ad9144_init_param = {
2, // jesd_xbar_lane0_sel
3, // jesd_xbar_lane1_sel
0, // jesd_xbar_lane2_sel
1, // jesd_xbar_lane3_sel

for the above case i find the mapping as follows 

logical_lane_0 at  ad9144 -> serdin 2 in daq2 -> phy lane 3 (tx_data_p[3]).

logical_lane_1 at  ad9144 -> serdin 3 in daq2 -> phy lane 1 (tx_data_p[1])

logical_lane_2 at  ad9144 -> serdin 0 in daq2 -> phy lane 0 (tx_data_p[0])

logical_lane_3 at  ad9144 -> serdin 1 in daq2 -> phy lane 2 (tx_data_p[2])


I think only Phy lane 0 is correctly mapped, can someone please clarify?