I want to clock a Sharc 21469 from a 48kHz AES signal and synchronously drive an 8 channel TDM codec.
The codec needs a bit clock of 12.288 MHz and a frame sync signal which rises at the negative edge of the bit clock (see attachment)
The analog output signals must be in sync with the incoming AES, so I need to derive everything from the recovered AES clock.That means I am limited to the 12.288 MHz DIR_TDMCLK_O signal which prevents me from using frame sync phase since I'd need a half period clock shift which is not possible.
I then went for using one-shot bypass mode in the FS generator but got stuck there, too. I can have the frame sync start at the negative edge of the triggering frame sync signal but not at the negative edge of the pulse width signal of MISCA2_I.
So, unless somebody points me into a direction which I have overlooked, it seems not to be possible what I want to achieve.