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ADM1270. Is there are any restrictions to use this controller in N 1 power redundancy?

Question asked by nt41 on Jan 13, 2017

ADM1270. Is there are any restrictions to use this controller in N+1 power redundancy?

In datasheet I found no details about pull-up pull-down mechanics in gate control of Q1 & Q2.

Only found such parts:

"

An undervoltage event is detected when the voltage

connected to the UV pin falls below 1 V, and the FET is turned

off using the 10 mA pull-up current. Similarly, when an overvoltage

event occurs and the voltage on the OV pin exceeds 1 V, the

FET is turned off using the 10 mA pull-up current.

"

Current sources in GS of Q2?

"

When VCC is connected to the input supply, the internal supply

(VCAP) of the ADM1270 must charge up. VCAP starts up and

settles in a very short time. When the UVLO threshold voltage is

exceeded at VCAP, the device emerges from reset. During this first

brief reset period, the GATE and TIMER pins are both held low.

"

LOW to WHAT?

or just shunt Vgs of Q2 to zero voltage drop?

Thanks!

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