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ADRV9371 / AD9528 configuration 10MHz reference

Question asked by paunderb on Jan 13, 2017

Using the following configuration:

Register 0x0109 bit 2 = 0: PLL1 Feedback Divider Source; 0 selects the PLL2 feedback divider

Register 0x010A bit 3 = 1 VCXO_CTRL control voltage goes to VCC/2.

 

R1 = 3; N1 = 512; Ra=125; 

VCXO = 10*(R1*N1/Ra) = 122.88MHz 

 

PLL 1 PFD input frequency is 80KHz 

Does the loop bandwidth or charge pump current need to be changed?

 

 


 

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