I am setting up AD9681 with HSC-ADC-EVALDZ. I have followed the instructions from the manual but get a Read cannot be performed because FIFO is not ready for feedback error.
Its fixed now. Thanks for your help.
Thank you very much for looking at the AD9681. I'm sorry about the trouble you are having.
Thank you very much.
I restarted the boards and the error has gone away, however, the visual analog is displaying a sawtooth wave in the samples example. Even if I disconnect the AD9681 the same sawtooth wave is generated. I think the HSC-ADC-EVALDZ is not connecting to AD9681.
Thank you for the information. When you "disconnect the AD9681", are you disconnecting the AD9681 board from the FPGA board, or are you disconnecting your signal source from the AD9681, or ??
What code swing are you seeing in the sawtooth? Is it possible for you to attach a picture of the waveform?
You can save the graph picture in VisualAnalog by clicking the upper left button in the graph window, then navigate File --> Save Form As . . . Then you can choose a filename and save it in a picture format. You could also just do a screen copy.
First I disconnected the signal, same graph was seen. Then I powered off AD9681 board and same graph was seen. There is no error that AD9681 is not connected.
Good work! I'm very glad your problem is resolved.
Can you share what you did to get it working, and what the problem was? This could help others on EngineerZone.
In Visual Analog, Data capture settings programmed the FPGA again.
Thank you Wardah. I hope your project goes well.
Retrieving data ...