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clock distribution device recommendation

Question asked by TripleX on Sep 10, 2011
Latest reply on Sep 14, 2011 by pkern

Dear people,


This is a request for the recommendation of a PLL based clock distribution chip of some kind that is right for my application.


I have a microcontroller that can address external memory or FPGA-based peripheral registers. The intention is to interface the MCU bus to the FPGA. The bus consists of an 16 bit multiplexed address and data bus, 16 MHz clock, R/W signal and a few other control signals. Addressing FPGA-based peripheral registers wouldn’t be that hard, but addressing FPGA embedded memory is likely to be impossible because I need a few more clock cycles to get the job done, especially during a read cycle on the bus. Therefore I was thinking about using an PLL to create a multiplied version of the 16 MHz MCU clock. Let’s call the 16 MHz clock signal provided by the MCU the “MCU_CLK”. The PLL multiplies it with 10 (or something like that), the resulting clock is called “MCU_CLK10X”. In the FPGA I make a counter that is clocked with MCU_CLK10X, starts with 0 when a rising transition is detected on MCU_CLK, and counts up on every rising edge of MCU_CLK10X. This counter gives me information of the phase of MCU_CLK to do the actual reads and writes on the bus. Note: I’m certainly willing to explain this better or from another perspective if you need to. Please ask where you need more information about.


Regrettably I cannot use the PLL resources of the FPGA because 16 MHz is too low. It is designed for an input clock from 25 MHz. Now I am looking for a external PLL approach. Besides the generated MCU_CLK10X I also want the device to output another 16 MHz version of the MCU_CLK to be able to implement the counter in the FPGA. As splitting clock nets on the PCB is a bad idea. So, I think specifically for my application it is important to know the phase relationship between the input clock and the output clock. For example: Can you align a rising edge of the input clock with an rising edge of the output clock. Maybe the “AD9552 Oscillator Frequency Up Converter” is a good device for my application but I wasn’t able to find information in the datasheet about the phase relationship I just mentioned.


Below is a summary of the functionality I think I need.
• Integer frequency multiplication (up to 25).
• Known phase relationship between input and output clocks.
• Suitable for an single ended CMOS (3.3V) input clock of 16 MHz.
• The MCU clock has some jitter, 100 ps peak-peak or more. Could the PLL generated clock have better jitter performance?
• ≥3 LVPECL outputs each with programmable dividers and phase adjust.


Which device do you recommend? And where can I read about the phase relationship between input and output clocks?


Thank you for your effort!