AnsweredAssumed Answered

AD9910 eval board external ramp control

Question asked by deconite on Jan 12, 2017
Latest reply on Jan 30, 2017 by JLKeip

So I'm trying to us the DDS ramp control to shift the clock frequency of a PLL, and I'd like to do that with one of our TTL channels.  Looking at the board design and the way the ramps are defined and controlled I decided cutting the leads between the ALTERA controller would prevent a voltage applied to the DR_CTL pins from destroying the controller.  This is something I can repair, and I could also put in a resistor to limit the current the ALTERA controller eats.  


When I attempt to use the software to set up a digital ramp, even if I'm not applying a signal to DR_CTL, the software immediately indicates the ramp is complete, and looking at the output on a spectrum analyzer I can tell the frequency has not changed at all.  If I try to drive it with a 2s period square wave nothing happens.


I couldn't find anything that indicates the limit of a step size in the ramp in either time or frequency, although the program appears to bottom out at .47 Hz steps when I use a 1GHz clock.  In my first attempt I was going for a ramp from 2 to 2.001 MHz in ~1Hz steps at 100 us intervals.


Does anyone know how I have screwed this up?